\doxysection{RCC\+\_\+\+Clk\+Init\+Type\+Def Struct Reference}
\hypertarget{struct_r_c_c___clk_init_type_def}{}\label{struct_r_c_c___clk_init_type_def}\index{RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}}


RCC System, AHB and APB busses clock configuration structure definition.  




{\ttfamily \#include $<$stm32h7xx\+\_\+hal\+\_\+rcc.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___clk_init_type_def_a93a53676a1cfc5b55b8b990e7ff4dac5}{Clock\+Type}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___clk_init_type_def_a4ceff1fdbf423e347c63052ca2c1d7e1}{SYSCLKSource}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___clk_init_type_def_aa49663a5d76af14424c7d1c3525b9381}{SYSCLKDivider}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___clk_init_type_def_abd9bcaa8dcf4b816462ee2930ab3e993}{AHBCLKDivider}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___clk_init_type_def_aabb6ee5533a966785511f3d09bcf255d}{APB3\+CLKDivider}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___clk_init_type_def_a21ceb024102adc3c4dc7eb270cf02ebd}{APB1\+CLKDivider}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___clk_init_type_def_aa75c110cd93855d49249f38da8cf94f7}{APB2\+CLKDivider}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___clk_init_type_def_a2ad661dc89d2d18b5e31d7d2c8d33de8}{APB4\+CLKDivider}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
RCC System, AHB and APB busses clock configuration structure definition. 

\label{doc-variable-members}
\Hypertarget{struct_r_c_c___clk_init_type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_r_c_c___clk_init_type_def_abd9bcaa8dcf4b816462ee2930ab3e993}\index{RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}!AHBCLKDivider@{AHBCLKDivider}}
\index{AHBCLKDivider@{AHBCLKDivider}!RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{AHBCLKDivider}{AHBCLKDivider}}
{\footnotesize\ttfamily \label{struct_r_c_c___clk_init_type_def_abd9bcaa8dcf4b816462ee2930ab3e993} 
uint32\+\_\+t RCC\+\_\+\+Clk\+Init\+Type\+Def\+::\+AHBCLKDivider}

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of \doxylink{group___r_c_c___h_c_l_k___clock___source}{RCC HCLK Clock Source} \Hypertarget{struct_r_c_c___clk_init_type_def_a21ceb024102adc3c4dc7eb270cf02ebd}\index{RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}!APB1CLKDivider@{APB1CLKDivider}}
\index{APB1CLKDivider@{APB1CLKDivider}!RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{APB1CLKDivider}{APB1CLKDivider}}
{\footnotesize\ttfamily \label{struct_r_c_c___clk_init_type_def_a21ceb024102adc3c4dc7eb270cf02ebd} 
uint32\+\_\+t RCC\+\_\+\+Clk\+Init\+Type\+Def\+::\+APB1\+CLKDivider}

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of \doxylink{group___r_c_c___a_p_b1___clock___source}{RCC APB1 Clock Source} \Hypertarget{struct_r_c_c___clk_init_type_def_aa75c110cd93855d49249f38da8cf94f7}\index{RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}!APB2CLKDivider@{APB2CLKDivider}}
\index{APB2CLKDivider@{APB2CLKDivider}!RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{APB2CLKDivider}{APB2CLKDivider}}
{\footnotesize\ttfamily \label{struct_r_c_c___clk_init_type_def_aa75c110cd93855d49249f38da8cf94f7} 
uint32\+\_\+t RCC\+\_\+\+Clk\+Init\+Type\+Def\+::\+APB2\+CLKDivider}

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of \doxylink{group___r_c_c___a_p_b2___clock___source}{RCC APB2 Clock Source} \Hypertarget{struct_r_c_c___clk_init_type_def_aabb6ee5533a966785511f3d09bcf255d}\index{RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}!APB3CLKDivider@{APB3CLKDivider}}
\index{APB3CLKDivider@{APB3CLKDivider}!RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{APB3CLKDivider}{APB3CLKDivider}}
{\footnotesize\ttfamily \label{struct_r_c_c___clk_init_type_def_aabb6ee5533a966785511f3d09bcf255d} 
uint32\+\_\+t RCC\+\_\+\+Clk\+Init\+Type\+Def\+::\+APB3\+CLKDivider}

The APB3 clock (D1\+PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of \doxylink{group___r_c_c___a_p_b3___clock___source}{RCC APB3 Clock Source} \Hypertarget{struct_r_c_c___clk_init_type_def_a2ad661dc89d2d18b5e31d7d2c8d33de8}\index{RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}!APB4CLKDivider@{APB4CLKDivider}}
\index{APB4CLKDivider@{APB4CLKDivider}!RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{APB4CLKDivider}{APB4CLKDivider}}
{\footnotesize\ttfamily \label{struct_r_c_c___clk_init_type_def_a2ad661dc89d2d18b5e31d7d2c8d33de8} 
uint32\+\_\+t RCC\+\_\+\+Clk\+Init\+Type\+Def\+::\+APB4\+CLKDivider}

The APB4 clock (D3\+PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of \doxylink{group___r_c_c___a_p_b4___clock___source}{RCC APB4 Clock Source} \Hypertarget{struct_r_c_c___clk_init_type_def_a93a53676a1cfc5b55b8b990e7ff4dac5}\index{RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}!ClockType@{ClockType}}
\index{ClockType@{ClockType}!RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{ClockType}{ClockType}}
{\footnotesize\ttfamily \label{struct_r_c_c___clk_init_type_def_a93a53676a1cfc5b55b8b990e7ff4dac5} 
uint32\+\_\+t RCC\+\_\+\+Clk\+Init\+Type\+Def\+::\+Clock\+Type}

The clock to be configured. This parameter can be a value of \doxylink{group___r_c_c___system___clock___type}{RCC System Clock Type} \Hypertarget{struct_r_c_c___clk_init_type_def_aa49663a5d76af14424c7d1c3525b9381}\index{RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}!SYSCLKDivider@{SYSCLKDivider}}
\index{SYSCLKDivider@{SYSCLKDivider}!RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{SYSCLKDivider}{SYSCLKDivider}}
{\footnotesize\ttfamily \label{struct_r_c_c___clk_init_type_def_aa49663a5d76af14424c7d1c3525b9381} 
uint32\+\_\+t RCC\+\_\+\+Clk\+Init\+Type\+Def\+::\+SYSCLKDivider}

The system clock divider. This parameter can be a value of \doxylink{group___r_c_c___s_y_s___clock___source}{RCC SYS Clock Source} \Hypertarget{struct_r_c_c___clk_init_type_def_a4ceff1fdbf423e347c63052ca2c1d7e1}\index{RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}!SYSCLKSource@{SYSCLKSource}}
\index{SYSCLKSource@{SYSCLKSource}!RCC\_ClkInitTypeDef@{RCC\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{SYSCLKSource}{SYSCLKSource}}
{\footnotesize\ttfamily \label{struct_r_c_c___clk_init_type_def_a4ceff1fdbf423e347c63052ca2c1d7e1} 
uint32\+\_\+t RCC\+\_\+\+Clk\+Init\+Type\+Def\+::\+SYSCLKSource}

The clock source (SYSCLKS) used as system clock. This parameter can be a value of \doxylink{group___r_c_c___system___clock___source}{RCC System Clock Source} 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/\mbox{\hyperlink{stm32h7xx__hal__rcc_8h}{stm32h7xx\+\_\+hal\+\_\+rcc.\+h}}\end{DoxyCompactItemize}
